1. Field of the Invention
Embodiments of the present invention generally relate to silicide formation process and, more specifically, to applying a low-temperature ion implantation process to the silicide formation process.
2. Description of the Related Art
Silicides are formed by depositing a layer of metal on top of conductive silicon and then heating the structure to allow the metal and silicon to combine into a silicide. Silicides are especially useful in reducing resistance of conductive silicon. Oftentimes, the silicon material to be a silicided is subjected to an ion treatment to create an amorphized region. However, the borders of this amorphized region can contain irregularities (end-of-range damage) that can be undesirably filled with the conductive metal, resulting in short circuits. For example, a room temperature 15 keV xenon ion implantation process would cause an amorphization depth of 160 A, but the damage would extend 275 A into the substrate, potentially leading to short circuits.
Further, previous amorphization ion implantation processes on SiGe cannot be readily integrated in device structures due to the observed degradation on P-type field effect transistors (PFETs) with eSiGe. The degradation of performance suggests that the stress in the channel regions induced by eSiGe is partially relaxed due to the damage caused by prior pre-amorphization ion implantation processes.